lukajankovic/vivado-make
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fixed simulation target

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This commit is contained in:
Luka Jankovic 2023-10-13 03:49:53 +02:00
parent bb97d075c2
commit e995bab473
3 changed files with 11 additions and 6 deletions
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13
Makefile
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@ -11,14 +11,18 @@ WAVEFORM_CFG := $(SIM_DIR)/$(SIM_TOP).sim.wcfg
WAVEFORM_VCD := simulation_${PROJ_NAME}.wdb WAVEFORM_VCD := simulation_${PROJ_NAME}.wdb
all: sim
sim: $(WAVEFORM_VCD) sim: $(WAVEFORM_VCD)
$(WAVEFORM_VCD): $(SRC_DIR)/*.vhdl $(WAVEFORM_VCD): $(SRC_DIR)/*.vhdl
source $(VIVADO_SETTINGS) && \
cd $(BUILD_DIR) && \ cd $(BUILD_DIR) && \
xelab -debug typical $(SIM_TOP) -s $(SIM_TOP).sim && \ xelab -debug typical -top $(SIM_TOP) -snapshot $(SIM_TOP)_snapshot && \
xsim $(SIM_TOP).sim -gui -view ../$(WAVEFORM_CFG) xsim $(SIM_TOP)_snapshot -gui -view ../$(WAVEFORM_CFG)
$(SRC_DIR)/*.vhdl: $(BUILD_DIR) $(SRC_DIR)/*.vhdl: $(BUILD_DIR)
source $(VIVADO_SETTINGS) && \
cd $(BUILD_DIR) && \ cd $(BUILD_DIR) && \
xvhdl ../$(SRC_DIR)/*.vhdl ../$(SIM_DIR)/*.vhdl xvhdl ../$(SRC_DIR)/*.vhdl ../$(SIM_DIR)/*.vhdl
@ -26,5 +30,6 @@ $(BUILD_DIR):
source $(VIVADO_SETTINGS) && \ source $(VIVADO_SETTINGS) && \
mkdir -p $@ mkdir -p $@
.PHONY: clean
clean: clean:
rm -rf $(BUILD_DIR) *.log *.pb rm -rf $(BUILD_DIR) *.log *.pb *.jou *.wdb *.str xsim.dir .Xil

4
sim/example_tb.vhdl
View file

@ -6,7 +6,7 @@ end entity;
architecture behav of example_tb is architecture behav of example_tb is
component adder is component and_gate is
port( port(
x : in std_logic; x : in std_logic;
y : in std_logic; y : in std_logic;
@ -23,7 +23,7 @@ begin
x_in <= '1'; x_in <= '1';
y_in <= '0'; y_in <= '0';
U1 : adder port map ( U1 : and_gate port map (
x => x_in, x => x_in,
y => y_in, y => y_in,
z => z_out z => z_out

0
src/adder.vhdl → src/and_gate.vhdl
View file