diff --git a/Makefile b/Makefile
index 93d582d..5e46a27 100644
--- a/Makefile
+++ b/Makefile
@@ -11,14 +11,18 @@ WAVEFORM_CFG := $(SIM_DIR)/$(SIM_TOP).sim.wcfg
 
 WAVEFORM_VCD := simulation_${PROJ_NAME}.wdb
 
+all: sim
+
 sim: $(WAVEFORM_VCD)
 
 $(WAVEFORM_VCD): $(SRC_DIR)/*.vhdl
+	source $(VIVADO_SETTINGS) && \
 	cd $(BUILD_DIR) && \
-	xelab -debug typical $(SIM_TOP) -s $(SIM_TOP).sim && \
-	xsim $(SIM_TOP).sim -gui -view ../$(WAVEFORM_CFG)
+	xelab -debug typical -top $(SIM_TOP) -snapshot $(SIM_TOP)_snapshot && \
+	xsim $(SIM_TOP)_snapshot -gui -view ../$(WAVEFORM_CFG)
 
-$(SRC_DIR)/*.vhdl: $(BUILD_DIR)
+$(SRC_DIR)/*.vhdl: $(BUILD_DIR) 
+	source $(VIVADO_SETTINGS) && \
 	cd $(BUILD_DIR) && \
 	xvhdl ../$(SRC_DIR)/*.vhdl ../$(SIM_DIR)/*.vhdl
 
@@ -26,5 +30,6 @@ $(BUILD_DIR):
 	source $(VIVADO_SETTINGS) && \
 	mkdir -p $@
 
+.PHONY: clean
 clean:
-	rm -rf $(BUILD_DIR) *.log *.pb
\ No newline at end of file
+	rm -rf $(BUILD_DIR) *.log *.pb *.jou *.wdb *.str xsim.dir .Xil
\ No newline at end of file
diff --git a/sim/example_tb.vhdl b/sim/example_tb.vhdl
index ec4a0f3..0b94fee 100644
--- a/sim/example_tb.vhdl
+++ b/sim/example_tb.vhdl
@@ -6,7 +6,7 @@ end entity;
 
 architecture behav of example_tb is
     
-    component adder is
+    component and_gate is
         port(
             x : in std_logic;
             y : in std_logic;
@@ -23,7 +23,7 @@ begin
     x_in <= '1';
     y_in <= '0';
 
-    U1 : adder port map (
+    U1 : and_gate port map (
         x => x_in,
         y => y_in,
         z => z_out
diff --git a/src/adder.vhdl b/src/and_gate.vhdl
similarity index 100%
rename from src/adder.vhdl
rename to src/and_gate.vhdl