32 lines
No EOL
522 B
VHDL
32 lines
No EOL
522 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity example_tb is
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end entity;
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architecture behav of example_tb is
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component and_gate is
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port(
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x : in std_logic;
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y : in std_logic;
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z : out std_logic
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);
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end component;
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signal x_in : std_logic;
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signal y_in : std_logic;
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signal z_out : std_logic;
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begin
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x_in <= '1';
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y_in <= '0';
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U1 : and_gate port map (
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x => x_in,
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y => y_in,
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z => z_out
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);
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end architecture; |