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fixed simulation target

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This commit is contained in:
Luka Jankovic 2023-10-13 03:49:53 +02:00
parent bb97d075c2
commit e995bab473
3 changed files with 11 additions and 6 deletions
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4
sim/example_tb.vhdl
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@ -6,7 +6,7 @@ end entity;
architecture behav of example_tb is
component adder is
component and_gate is
port(
x : in std_logic;
y : in std_logic;
@ -23,7 +23,7 @@ begin
x_in <= '1';
y_in <= '0';
U1 : adder port map (
U1 : and_gate port map (
x => x_in,
y => y_in,
z => z_out