lukajankovic/vivado-make
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added sytnehsis stage

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This commit is contained in:
Luka Jankovic 2023-12-31 02:59:26 +01:00
parent e995bab473
commit 350735b6af
4 changed files with 224 additions and 1 deletions
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16
Makefile
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@ -1,7 +1,8 @@
VIVADO_SETTINGS := C:/Xilinx/Vivado/2023.1/settings64.sh
VIVADO_SETTINGS := C:/Xilinx/Vivado/2023.2/settings64.sh
PROJ_NAME := example
SIM_TOP := example_tb
TOP := and_gate
SRC_DIR := src
SIM_DIR := sim
@ -11,6 +12,11 @@ WAVEFORM_CFG := $(SIM_DIR)/$(SIM_TOP).sim.wcfg
WAVEFORM_VCD := simulation_${PROJ_NAME}.wdb
PART := xc7z020clg400-1
CONSTRAINTS := Zybo-Z7.xdc
THREADS := 16
all: sim
sim: $(WAVEFORM_VCD)
@ -30,6 +36,14 @@ $(BUILD_DIR):
source $(VIVADO_SETTINGS) && \
mkdir -p $@
synth: $(BUILD_DIR)/synthesize.tcl
source $(VIVADO_SETTINGS) && \
cd .build && \
vivado -mode batch -nojournal -source synthesize.tcl
$(BUILD_DIR)/synthesize.tcl: synthesize.tcl.in $(BUILD_DIR)
sed -e 's/{{THREADS}}/$(THREADS)/g; s/{{CONST}}/$(CONSTRAINTS)/g; s/{{PART}}/$(PART)/g; s/{{TOP}}/$(TOP)/g' $< > $@
.PHONY: clean
clean:
rm -rf $(BUILD_DIR) *.log *.pb *.jou *.wdb *.str xsim.dir .Xil