49 lines
No EOL
1.2 KiB
Makefile
49 lines
No EOL
1.2 KiB
Makefile
VIVADO_SETTINGS := C:/Xilinx/Vivado/2023.2/settings64.sh
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PROJ_NAME := example
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SIM_TOP := example_tb
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TOP := and_gate
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SRC_DIR := src
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SIM_DIR := sim
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BUILD_DIR := .build
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WAVEFORM_CFG := $(SIM_DIR)/$(SIM_TOP).sim.wcfg
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WAVEFORM_VCD := simulation_${PROJ_NAME}.wdb
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PART := xc7z020clg400-1
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CONSTRAINTS := Zybo-Z7.xdc
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THREADS := 16
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all: sim
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sim: $(WAVEFORM_VCD)
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$(WAVEFORM_VCD): $(SRC_DIR)/*.vhdl
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source $(VIVADO_SETTINGS) && \
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cd $(BUILD_DIR) && \
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xelab -debug typical -top $(SIM_TOP) -snapshot $(SIM_TOP)_snapshot && \
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xsim $(SIM_TOP)_snapshot -gui -view ../$(WAVEFORM_CFG)
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$(SRC_DIR)/*.vhdl: $(BUILD_DIR)
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source $(VIVADO_SETTINGS) && \
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cd $(BUILD_DIR) && \
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xvhdl ../$(SRC_DIR)/*.vhdl ../$(SIM_DIR)/*.vhdl
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$(BUILD_DIR):
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source $(VIVADO_SETTINGS) && \
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mkdir -p $@
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synth: $(BUILD_DIR)/synthesize.tcl
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source $(VIVADO_SETTINGS) && \
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cd .build && \
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vivado -mode batch -nojournal -source synthesize.tcl
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$(BUILD_DIR)/synthesize.tcl: synthesize.tcl.in $(BUILD_DIR)
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sed -e 's/{{THREADS}}/$(THREADS)/g; s/{{CONST}}/$(CONSTRAINTS)/g; s/{{PART}}/$(PART)/g; s/{{TOP}}/$(TOP)/g' $< > $@
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.PHONY: clean
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clean:
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rm -rf $(BUILD_DIR) *.log *.pb *.jou *.wdb *.str xsim.dir .Xil
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