lukajankovic/vivado-make
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Luka Jankovic a739b21b50 added readme
2024-01-14 02:05:40 +01:00
sim fixed simulation target 2023-10-13 03:49:53 +02:00
src fixed simulation target 2023-10-13 03:49:53 +02:00
.gitignore added sytnehsis stage 2023-12-31 02:59:26 +01:00
build.tcl.in changed synth to build 2024-01-14 02:05:22 +01:00
Makefile changed synth to build 2024-01-14 02:05:22 +01:00
program.tcl.in added program stage 2024-01-14 02:05:32 +01:00
README.md added readme 2024-01-14 02:05:40 +01:00
Zybo-Z7.xdc added implementation 2024-01-04 18:59:05 +01:00

README.md

vivado-make

Simple make system for simulating, synthesizing and routing VHDL projects as well as programming boards. Requires Vivado and doesn't rely on any other tools (apart from make, install with scoop on Windows)

Supports VHDL and the example is build for the Zybo-Z7 board.