init, starts simulation incorrectly

sim/example_tb.sim.wcfg

@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="example_tb.sim.wdb" id="1">
+         <top_modules>
+            <top_module name="example_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="9,703.994 ns"></ZoomStartTime>
+      <ZoomEndTime time="11,479.995 ns"></ZoomEndTime>
+      <Cursor1Time time="10,053.994 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="164"></NameColumnWidth>
+      <ValueColumnWidth column_width="168"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="3" />
+   <wvobject fp_name="/example_tb/x_in" type="logic">
+      <obj_property name="ElementShortName">x_in</obj_property>
+      <obj_property name="ObjectShortName">x_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/example_tb/y_in" type="logic">
+      <obj_property name="ElementShortName">y_in</obj_property>
+      <obj_property name="ObjectShortName">y_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/example_tb/z_out" type="logic">
+      <obj_property name="ElementShortName">z_out</obj_property>
+      <obj_property name="ObjectShortName">z_out</obj_property>
+   </wvobject>
+</wave_config>

sim/example_tb.vhdl

@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity example_tb is
+end entity;
+
+architecture behav of example_tb is
+    
+    component adder is
+        port(
+            x : in std_logic;
+            y : in std_logic;
+            z : out std_logic
+        );
+    end component;
+
+    signal x_in : std_logic;
+    signal y_in : std_logic;
+    signal z_out : std_logic;
+
+begin
+
+    x_in <= '1';
+    y_in <= '0';
+
+    U1 : adder port map (
+        x => x_in,
+        y => y_in,
+        z => z_out
+    );
+
+end architecture;