From bb97d075c276b3aa6ffe3440d01918f60ccc40e4 Mon Sep 17 00:00:00 2001
From: Luka Jankovic <lukjan1999@gmail.com>
Date: Wed, 11 Oct 2023 03:46:43 +0200
Subject: [PATCH] init, starts simulation incorrectly

---
 Makefile                | 30 ++++++++++++++++++++++++++++++
 sim/example_tb.sim.wcfg | 34 ++++++++++++++++++++++++++++++++++
 sim/example_tb.vhdl     | 32 ++++++++++++++++++++++++++++++++
 src/adder.vhdl          | 17 +++++++++++++++++
 4 files changed, 113 insertions(+)
 create mode 100644 Makefile
 create mode 100644 sim/example_tb.sim.wcfg
 create mode 100644 sim/example_tb.vhdl
 create mode 100644 src/adder.vhdl

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..93d582d
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,30 @@
+VIVADO_SETTINGS := C:/Xilinx/Vivado/2023.1/settings64.sh
+
+PROJ_NAME		:= example
+SIM_TOP			:= example_tb
+
+SRC_DIR			:= src
+SIM_DIR			:= sim
+BUILD_DIR		:= .build
+
+WAVEFORM_CFG := $(SIM_DIR)/$(SIM_TOP).sim.wcfg
+
+WAVEFORM_VCD := simulation_${PROJ_NAME}.wdb
+
+sim: $(WAVEFORM_VCD)
+
+$(WAVEFORM_VCD): $(SRC_DIR)/*.vhdl
+	cd $(BUILD_DIR) && \
+	xelab -debug typical $(SIM_TOP) -s $(SIM_TOP).sim && \
+	xsim $(SIM_TOP).sim -gui -view ../$(WAVEFORM_CFG)
+
+$(SRC_DIR)/*.vhdl: $(BUILD_DIR)
+	cd $(BUILD_DIR) && \
+	xvhdl ../$(SRC_DIR)/*.vhdl ../$(SIM_DIR)/*.vhdl
+
+$(BUILD_DIR):
+	source $(VIVADO_SETTINGS) && \
+	mkdir -p $@
+
+clean:
+	rm -rf $(BUILD_DIR) *.log *.pb
\ No newline at end of file
diff --git a/sim/example_tb.sim.wcfg b/sim/example_tb.sim.wcfg
new file mode 100644
index 0000000..a82ed38
--- /dev/null
+++ b/sim/example_tb.sim.wcfg
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="example_tb.sim.wdb" id="1">
+         <top_modules>
+            <top_module name="example_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="9,703.994 ns"></ZoomStartTime>
+      <ZoomEndTime time="11,479.995 ns"></ZoomEndTime>
+      <Cursor1Time time="10,053.994 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="164"></NameColumnWidth>
+      <ValueColumnWidth column_width="168"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="3" />
+   <wvobject fp_name="/example_tb/x_in" type="logic">
+      <obj_property name="ElementShortName">x_in</obj_property>
+      <obj_property name="ObjectShortName">x_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/example_tb/y_in" type="logic">
+      <obj_property name="ElementShortName">y_in</obj_property>
+      <obj_property name="ObjectShortName">y_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/example_tb/z_out" type="logic">
+      <obj_property name="ElementShortName">z_out</obj_property>
+      <obj_property name="ObjectShortName">z_out</obj_property>
+   </wvobject>
+</wave_config>
diff --git a/sim/example_tb.vhdl b/sim/example_tb.vhdl
new file mode 100644
index 0000000..ec4a0f3
--- /dev/null
+++ b/sim/example_tb.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity example_tb is
+end entity;
+
+architecture behav of example_tb is
+    
+    component adder is
+        port(
+            x : in std_logic;
+            y : in std_logic;
+            z : out std_logic
+        );
+    end component;
+
+    signal x_in : std_logic;
+    signal y_in : std_logic;
+    signal z_out : std_logic;
+
+begin
+
+    x_in <= '1';
+    y_in <= '0';
+
+    U1 : adder port map (
+        x => x_in,
+        y => y_in,
+        z => z_out
+    );
+
+end architecture;
\ No newline at end of file
diff --git a/src/adder.vhdl b/src/adder.vhdl
new file mode 100644
index 0000000..1386fbd
--- /dev/null
+++ b/src/adder.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity and_gate is
+    port(
+        x : in std_logic;
+        y : in std_logic;
+        z : out std_logic
+    );
+end entity;
+
+architecture behav of and_gate is
+    signal a : std_logic;
+begin
+    a <= x;
+    z <= a and y;
+end architecture;
\ No newline at end of file