78 lines
2 KiB
VHDL
78 lines
2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity ssd_top is
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port(
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clk : in std_logic;
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sw : in std_logic_vector(3 downto 0);
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btn : in std_logic_vector(3 downto 0);
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led : out std_logic_vector(3 downto 0);
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jb : out std_logic_vector(7 downto 0);
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jc : out std_logic_vector(7 downto 0);
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jd : out std_logic_vector(7 downto 0);
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je : out std_logic_vector(7 downto 0)
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);
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end entity;
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architecture behav of ssd_top is
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component pmod_ssd is
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port(
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clk : in std_logic;
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digit_in : in std_logic_vector(3 downto 0);
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digit_sel : in std_logic;
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digit_write : in std_logic;
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header_1 : out std_logic_vector(3 downto 0);
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header_2 : out std_logic_vector(3 downto 0)
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);
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end component;
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signal pmod_1_digit_sel : std_logic;
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signal pmod_1_digit_write : std_logic;
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signal pmod_2_digit_sel : std_logic;
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signal pmod_2_digit_write : std_logic;
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signal ssd_out_1 : std_logic_vector(7 downto 0);
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signal ssd_out_2 : std_logic_vector(7 downto 0);
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begin
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U1: pmod_ssd port map(
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clk,
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digit_in => sw,
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digit_sel => pmod_1_digit_sel,
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digit_write => pmod_1_digit_write,
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header_1 => ssd_out_1(7 downto 4),
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header_2 => ssd_out_1(3 downto 0)
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);
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U2: pmod_ssd port map(
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clk,
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digit_in => sw,
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digit_sel => pmod_2_digit_sel,
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digit_write => pmod_2_digit_write,
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header_1 => ssd_out_2(7 downto 4),
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header_2 => ssd_out_2(3 downto 0)
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);
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jb(3 downto 0) <= ssd_out_1(7 downto 4);
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jc(3 downto 0) <= ssd_out_1(3 downto 0);
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jd(3 downto 0) <= ssd_out_2(7 downto 4);
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je(3 downto 0) <= ssd_out_2(3 downto 0);
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led <= sw;
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pmod_1_digit_sel <= btn(1);
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pmod_1_digit_write <= btn(0) or btn(1);
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pmod_2_digit_sel <= btn(3);
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pmod_2_digit_write <= btn(3) or btn(2);
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end architecture;
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