library ieee;
use ieee.std_logic_1164.all;

entity ssd_top is

    port(
        clk : in std_logic;
        sw  : in std_logic_vector(3 downto 0);
        btn : in std_logic_vector(3 downto 0);

        led : out std_logic_vector(3 downto 0);
        jb  : out std_logic_vector(7 downto 0);
        jc  : out std_logic_vector(7 downto 0);
        jd  : out std_logic_vector(7 downto 0);
        je  : out std_logic_vector(7 downto 0)
    );

end entity;

architecture behav of ssd_top is

    component pmod_ssd is
        port(
            clk         : in std_logic;
            digit_in    : in std_logic_vector(3 downto 0);
            digit_sel   : in std_logic;
            digit_write : in std_logic;

            header_1    : out std_logic_vector(3 downto 0);
            header_2    : out std_logic_vector(3 downto 0)
        );
    end component;

    signal pmod_1_digit_sel : std_logic;
    signal pmod_1_digit_write : std_logic;
    signal pmod_2_digit_sel : std_logic;
    signal pmod_2_digit_write : std_logic;

    signal ssd_out_1 : std_logic_vector(7 downto 0);
    signal ssd_out_2 : std_logic_vector(7 downto 0);

begin

    U1: pmod_ssd port map(
        clk,
        digit_in => sw,
        digit_sel => pmod_1_digit_sel,
        digit_write => pmod_1_digit_write,
        
        header_1 => ssd_out_1(7 downto 4),
        header_2 => ssd_out_1(3 downto 0)
    );

    U2: pmod_ssd port map(
        clk,
        digit_in => sw,
        digit_sel => pmod_2_digit_sel,
        digit_write => pmod_2_digit_write,
        
        header_1 => ssd_out_2(7 downto 4),
        header_2 => ssd_out_2(3 downto 0)
    );

    jb(3 downto 0) <= ssd_out_1(7 downto 4);
    jc(3 downto 0) <= ssd_out_1(3 downto 0);

    jd(3 downto 0) <= ssd_out_2(7 downto 4);
    je(3 downto 0) <= ssd_out_2(3 downto 0);

    led <= sw;

    pmod_1_digit_sel <= btn(1);
    pmod_1_digit_write <= btn(0) or btn(1);

    pmod_2_digit_sel <= btn(3);
    pmod_2_digit_write <= btn(3) or btn(2);

end architecture;