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sim
|
fixed simulation target
|
2023-10-13 03:49:53 +02:00 |
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src
|
fixed simulation target
|
2023-10-13 03:49:53 +02:00 |
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.gitignore
|
added sytnehsis stage
|
2023-12-31 02:59:26 +01:00 |
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Makefile
|
added sytnehsis stage
|
2023-12-31 02:59:26 +01:00 |
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synthesize.tcl.in
|
added implementation
|
2024-01-04 18:59:05 +01:00 |
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Zybo-Z7.xdc
|
added implementation
|
2024-01-04 18:59:05 +01:00 |
