lukajankovic/vivado-make
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Luka Jankovic 2d6563a3cf move all project variables to env, update readme
2025-11-12 21:23:24 +01:00
sim fixed simulation target 2023-10-13 03:49:53 +02:00
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.env move all project variables to env, update readme 2025-11-12 21:23:24 +01:00
.gitignore added sytnehsis stage 2023-12-31 02:59:26 +01:00
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Makefile move all project variables to env, update readme 2025-11-12 21:23:24 +01:00
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README.md move all project variables to env, update readme 2025-11-12 21:23:24 +01:00
Zybo-Z7.xdc added implementation 2024-01-04 18:59:05 +01:00

README.md

vivado-make

Simple make system for simulating, synthesizing and routing VHDL projects as well as programming boards. Requires Vivado and doesn't rely on any other tools (apart from make, install with scoop on Windows)

Supports VHDL and the example is built for the Zybo-Z7 board.

Usage

Only the .env file should need to be edited.

# Simulate
make sim

# Synth, opt, route design
make build

# Program target
make prog

Programming might require additional dependencies, such as Digilent Adept.