From fab7ff9ab952d97f1a71c3ad245647b873a1a614 Mon Sep 17 00:00:00 2001
From: Luka Jankovic <lukjan1999@gmail.com>
Date: Thu, 4 Jan 2024 18:59:05 +0100
Subject: [PATCH] added implementation

---
 Zybo-Z7.xdc       | 12 ++++++------
 synthesize.tcl.in | 21 ++++++++++++++++++++-
 2 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/Zybo-Z7.xdc b/Zybo-Z7.xdc
index c660d49..3fc0231 100644
--- a/Zybo-Z7.xdc
+++ b/Zybo-Z7.xdc
@@ -12,8 +12,8 @@ create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { cl
 
 
 ##Switches
-#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
-#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
+set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { x }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
+set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { y }]; #IO_L24P_T3_34 Sch=sw[1]
 #set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
 #set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
 
@@ -26,10 +26,10 @@ create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { cl
 
 
 #LEDs
-set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
-set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
-set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
-set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
+set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { z }]; #IO_L23P_T3_35 Sch=led[0]
+#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
 
 
 ##RGB LED 5 (Zybo Z7-20 only)
diff --git a/synthesize.tcl.in b/synthesize.tcl.in
index 26a7f09..d6bec8d 100644
--- a/synthesize.tcl.in
+++ b/synthesize.tcl.in
@@ -3,4 +3,23 @@ read_vhdl [glob ../src/*.vhdl]
 read_xdc ../{{CONST}}
 synth_design -part {{PART}} -top {{TOP}}
 write_checkpoint -force post_synth.dcp
-report_timing_summary -file timing_syn.rpt
\ No newline at end of file
+report_timing_summary -file timing_syn.rpt
+
+opt_design
+place_design
+phys_opt_design
+write_checkpoint -force post_place
+report_timing_summary -file post_place_timing_summary.rpt
+
+route_design
+write_checkpoint -force post_route
+report_timing_summary -file post_route_timing_summary.rpt
+report_timing -sort_by group -max_paths 100 -path_type summary -file post_route_timing.rpt
+report_clock_utilization -file clock_util.rpt
+report_utilization -file post_route_util.rpt
+report_power -file post_route_power.rpt
+report_drc -file post_imp_drc.rpt
+write_verilog -force bft_impl_netlist.v
+write_xdc -no_fixed_only -force bft_impl.xdc
+
+write_bitstream -force bft.bit
\ No newline at end of file