lukajankovic/vivado-make
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

move all project variables to env, update readme

Browse source
This commit is contained in:
Luka Jankovic 2025-11-12 21:23:24 +01:00
parent 2227c52371
commit 2d6563a3cf
3 changed files with 34 additions and 17 deletions
Download patch file Download diff file Expand all files Collapse all files

15
.env
View file

@ -1 +1,16 @@
VIVADO_SETTINGS=/opt/Xilinx/2025.1/Vivado/settings64.sh
PROJ_NAME=example
SIM_TOP=example_tb
TOP=and_gate
SRC_DIR=src
SIM_DIR=sim
BUILD_DIR=.build
WAVEFORM_CFG=$(SIM_DIR)/$(SIM_TOP).sim.wcfg
WAVEFORM_VCD=simulation_${PROJ_NAME}.wdb
PART=xc7z020clg400-1
CONSTRAINTS=Zybo-Z7.xdc

17
Makefile
View file

@ -1,22 +1,7 @@
include .env
export $(shell sed 's/=.*//' .env)
PROJ_NAME := example
SIM_TOP := example_tb
TOP := and_gate
SRC_DIR := src
SIM_DIR := sim
BUILD_DIR := .build
WAVEFORM_CFG := $(SIM_DIR)/$(SIM_TOP).sim.wcfg
WAVEFORM_VCD := simulation_${PROJ_NAME}.wdb
PART := xc7z020clg400-1
CONSTRAINTS := Zybo-Z7.xdc
THREADS := 16
THREADS := $(shell nproc)
all: sim

19
README.md
View file

@ -2,4 +2,21 @@
Simple make system for simulating, synthesizing and routing VHDL projects as well as programming boards. Requires Vivado and doesn't rely on any other tools (apart from `make`, install with `scoop` on Windows)
Supports VHDL and the example is build for the Zybo-Z7 board.
Supports VHDL and the example is built for the Zybo-Z7 board.
## Usage
Only the `.env` file should need to be edited.
```
# Simulate
make sim
# Synth, opt, route design
make build
# Program target
make prog
```
Programming might require additional dependencies, such as Digilent Adept.