move all project variables to env, update readme

.env

@@ -1 +1,16 @@
 VIVADO_SETTINGS=/opt/Xilinx/2025.1/Vivado/settings64.sh
+
+PROJ_NAME=example
+SIM_TOP=example_tb
+TOP=and_gate
+
+SRC_DIR=src
+SIM_DIR=sim
+BUILD_DIR=.build
+
+WAVEFORM_CFG=$(SIM_DIR)/$(SIM_TOP).sim.wcfg
+
+WAVEFORM_VCD=simulation_${PROJ_NAME}.wdb
+
+PART=xc7z020clg400-1
+CONSTRAINTS=Zybo-Z7.xdc

Makefile

@@ -1,22 +1,7 @@
 include .env
 export $(shell sed 's/=.*//' .env)
 
-PROJ_NAME		:= example
+THREADS := $(shell nproc)
-SIM_TOP			:= example_tb
-TOP				:= and_gate
-
-SRC_DIR			:= src
-SIM_DIR			:= sim
-BUILD_DIR		:= .build
-
-WAVEFORM_CFG := $(SIM_DIR)/$(SIM_TOP).sim.wcfg
-
-WAVEFORM_VCD := simulation_${PROJ_NAME}.wdb
-
-PART		:= xc7z020clg400-1
-CONSTRAINTS	:= Zybo-Z7.xdc
-
-THREADS		:= 16
 
 all: sim
 

README.md

@@ -2,4 +2,21 @@
 
 Simple make system for simulating, synthesizing and routing VHDL projects as well as programming boards. Requires Vivado and doesn't rely on any other tools (apart from `make`, install with `scoop` on Windows)
 
-Supports VHDL and the example is build for the Zybo-Z7 board.
+Supports VHDL and the example is built for the Zybo-Z7 board.
+
+## Usage
+
+Only the `.env` file should need to be edited.
+
+```
+# Simulate
+make sim
+
+# Synth, opt, route design
+make build
+
+# Program target
+make prog
+```
+
+Programming might require additional dependencies, such as Digilent Adept.