move all project variables to env, update readme

README.md

@@ -2,4 +2,21 @@
 
 Simple make system for simulating, synthesizing and routing VHDL projects as well as programming boards. Requires Vivado and doesn't rely on any other tools (apart from `make`, install with `scoop` on Windows)
 
-Supports VHDL and the example is build for the Zybo-Z7 board.
+Supports VHDL and the example is built for the Zybo-Z7 board.
+
+## Usage
+
+Only the `.env` file should need to be edited.
+
+```
+# Simulate
+make sim
+
+# Synth, opt, route design
+make build
+
+# Program target
+make prog
+```
+
+Programming might require additional dependencies, such as Digilent Adept.