34 lines
563 B
VHDL
34 lines
563 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity uart_tb is
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end entity;
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architecture behav of uart_tb is
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component uart_top is
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port(
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clk : in std_logic;
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in_send : in std_logic;
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out_txd : out std_logic
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);
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end component;
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signal clk : std_logic := '0';
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signal in_send : std_logic := '0';
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signal out_txd : std_logic;
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begin
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clk <= not clk after 4 ns;
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in_send <= '1' after 16 ns;
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U1: uart_top port map(
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clk,
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in_send,
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out_txd
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);
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end architecture;
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