| .. | ||
| sim | ||
| src | ||
| .env | ||
| build.tcl.in | ||
| Makefile | ||
| program.tcl.in | ||
| README.md | ||
| Zybo-Z7.xdc | ||
Pmod SSD
VHDL implementation for the seven segment display Pmod by Digilent. Takes a digit (4 bits) as input as well as output digit selection and write enable. The digits are stored in a register so they do not need to be continuously fed. Clock input is divided to ensure both digits are displayed properly. The output can be mapped directly to the Pmod headers. Testbench unused.