library ieee;
use ieee.std_logic_1164.all;

entity uart_tb is
end entity;

architecture behav of uart_tb is

    component uart_top is

        port(
            clk : in std_logic;
            in_send : in std_logic;
            out_txd : out std_logic
        );

    end component;

    signal clk : std_logic := '0';
    signal in_send : std_logic := '0';
    signal out_txd : std_logic;

begin

    clk <= not clk after 4 ns;
    in_send <= '1' after 16 ns;

    U1: uart_top port map(
        clk,
        in_send,
        out_txd
    );

end architecture;