init pmod uart txd
This commit is contained in:
parent
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commit
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12 changed files with 522 additions and 3 deletions
3
ssd/.gitignore
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3
ssd/.gitignore
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@ -1,3 +0,0 @@
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**/.build/
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**/vivado*.jou
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**/vivado*.log
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16
uart/.env
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16
uart/.env
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VIVADO_SETTINGS=/opt/Xilinx/2025.1/Vivado/settings64.sh
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PROJ_NAME=pmod_uart
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SIM_TOP=uart_tb
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TOP=uart_top
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SRC_DIR=src
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SIM_DIR=sim
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BUILD_DIR=.build
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WAVEFORM_CFG=$(SIM_DIR)/$(SIM_TOP).sim.wcfg
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WAVEFORM_VCD=simulation_${PROJ_NAME}.wdb
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PART=xc7z020clg400-1
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CONSTRAINTS=Zybo-Z7.xdc
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48
uart/Makefile
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48
uart/Makefile
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include .env
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export $(shell sed 's/=.*//' .env)
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THREADS := $(shell nproc)
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all: sim
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sim: $(WAVEFORM_VCD)
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$(WAVEFORM_VCD): $(SRC_DIR)/*.vhdl
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source $(VIVADO_SETTINGS) && \
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cd $(BUILD_DIR) && \
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xelab -debug typical -top $(SIM_TOP) -snapshot $(SIM_TOP)_snapshot && \
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xsim $(SIM_TOP)_snapshot -gui -view ../$(WAVEFORM_CFG)
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$(SRC_DIR)/*.vhdl: $(BUILD_DIR)
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source $(VIVADO_SETTINGS) && \
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cd $(BUILD_DIR) && \
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xvhdl ../$(SRC_DIR)/*.vhdl ../$(SIM_DIR)/*.vhdl
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$(BUILD_DIR):
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source $(VIVADO_SETTINGS) && \
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mkdir -p $@
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build: $(BUILD_DIR)/build.tcl
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source $(VIVADO_SETTINGS) && \
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cd .build && \
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vivado -mode batch -nojournal -source build.tcl
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program: $(BUILD_DIR)/program.tcl
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source $(VIVADO_SETTINGS) && \
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cd .build && \
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vivado -mode batch -nojournal -source program.tcl
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$(BUILD_DIR)/build.tcl: build.tcl.in $(BUILD_DIR)
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sed -e 's/{{THREADS}}/$(THREADS)/g' \
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-e 's/{{CONST}}/$(CONSTRAINTS)/g' \
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-e 's/{{PART}}/$(PART)/g' \
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-e 's/{{TOP}}/$(TOP)/g' \
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-e 's/{{PROJ}}/$(PROJ_NAME)/g' \
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-e 's/{{SRC}}/$(SRC_DIR)/g' $< > $@
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$(BUILD_DIR)/program.tcl: program.tcl.in $(BUILD_DIR)
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sed -e 's/{{PROJ}}/$(PROJ_NAME)/g' $< > $@
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.PHONY: clean
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clean:
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rm -rf $(BUILD_DIR) *.log *.pb *.jou *.wdb *.str xsim.dir .Xil
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3
uart/README.md
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3
uart/README.md
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# Pmod UART
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Writes 'E' on baud 115200 on button press.
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198
uart/Zybo-Z7.xdc
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198
uart/Zybo-Z7.xdc
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## This file is a general .xdc for the Zybo Z7 Rev. B
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## It is compatible with the Zybo Z7-20 and Zybo Z7-10
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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# ports used: clk, led, ja
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#Clock signal
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set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
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create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
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##Switches
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#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
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#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
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#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
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#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]
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##Buttons
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set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { in_send }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
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#set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
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#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
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#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]
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#LEDs
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set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
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set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
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#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
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#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]
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##RGB LED 5 (Zybo Z7-20 only)
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#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
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#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
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#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b
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##RGB LED 6
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#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
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#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
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#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b
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##Audio Codec
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#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_0_34 Sch=ac_bclk
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#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L19N_T3_VREF_34 Sch=ac_mclk
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#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=ac_muten
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#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L20N_T3_34 Sch=ac_pbdat
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#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_25_34 Sch=ac_pblrc
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#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L19P_T3_34 Sch=ac_recdat
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#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L17P_T2_34 Sch=ac_reclrc
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#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=ac_scl
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#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=ac_sda
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##Additional Ethernet signals
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#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { eth_int_pu_b }]; #IO_L6P_T0_35 Sch=eth_int_pu_b
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#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b
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##USB-OTG over-current detect pin
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#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=otg_oc
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##Fan (Zybo Z7-20 only)
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#set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { fan_fb_pu }]; #IO_L20N_T3_13 Sch=fan_fb_pu
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##HDMI RX
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#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd
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#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
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#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda
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#set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
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#set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
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#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
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#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
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#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
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#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
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#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
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#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]
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##HDMI RX CEC (Zybo Z7-20 only)
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#set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec
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##HDMI TX
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#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpd }]; #IO_L5P_T0_AD9P_35 Sch=hdmi_tx_hpd
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#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
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#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda
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#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
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#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
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#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
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#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
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#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
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#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
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#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
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#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]
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##HDMI TX CEC
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#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L5N_T0_AD9N_35 Sch=hdmi_tx_cec
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#Pmod Header JA (XADC)
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#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
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#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
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# set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
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#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
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#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
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#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
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#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
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#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
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##Pmod Header JB (Zybo Z7-20 only)
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#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]
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set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1]
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#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2]
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#set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2]
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#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3]
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#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L13N_T2_MRCC_13 Sch=jb_n[3]
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#set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L22P_T3_13 Sch=jb_p[4]
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#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L22N_T3_13 Sch=jb_n[4]
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##Pmod Header JC
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#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L10P_T1_34 Sch=jc_p[1]
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#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L10N_T1_34 Sch=jc_n[1]
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#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L1P_T0_34 Sch=jc_p[2]
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#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L1N_T0_34 Sch=jc_n[2]
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#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L8P_T1_34 Sch=jc_p[3]
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#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L8N_T1_34 Sch=jc_n[3]
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#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L2P_T0_34 Sch=jc_p[4]
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#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L2N_T0_34 Sch=jc_n[4]
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##Pmod Header JD
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#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L5P_T0_34 Sch=jd_p[1]
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#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L5N_T0_34 Sch=jd_n[1]
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#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L6P_T0_34 Sch=jd_p[2]
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#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L6N_T0_VREF_34 Sch=jd_n[2]
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#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L11P_T1_SRCC_34 Sch=jd_p[3]
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#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L11N_T1_SRCC_34 Sch=jd_n[3]
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#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L21P_T3_DQS_34 Sch=jd_p[4]
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#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L21N_T3_DQS_34 Sch=jd_n[4]
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##Pmod Header JE
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#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=je[1]
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#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=je[2]
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=je[3]
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=je[4]
|
||||
#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=je[7]
|
||||
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=je[8]
|
||||
#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=je[9]
|
||||
#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=je[10]
|
||||
|
||||
|
||||
##Pcam MIPI CSI-2 Connector
|
||||
## This configuration expects the sensor to use 672Mbps/lane = 336 MHz HS_Clk
|
||||
#create_clock -period 2.976 -name dphy_hs_clock_clk_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]
|
||||
#set_property INTERNAL_VREF 0.6 [get_iobanks 35]
|
||||
#set_property -dict { PACKAGE_PIN J19 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_n }]; #IO_L10N_T1_AD11N_35 Sch=lp_clk_n
|
||||
#set_property -dict { PACKAGE_PIN H20 IOSTANDARD HSUL_12 } [get_ports { dphy_clk_lp_p }]; #IO_L17N_T2_AD5N_35 Sch=lp_clk_p
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[0] }]; #IO_L8N_T1_AD10N_35 Sch=lp_lane_n[0]
|
||||
#set_property -dict { PACKAGE_PIN L19 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[0] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=lp_lane_p[0]
|
||||
#set_property -dict { PACKAGE_PIN L20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_n[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=lp_lane_n[1]
|
||||
#set_property -dict { PACKAGE_PIN J20 IOSTANDARD HSUL_12 } [get_ports { dphy_data_lp_p[1] }]; #IO_L17P_T2_AD5P_35 Sch=lp_lane_p[1]
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_n }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=mipi_clk_n
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVDS_25 } [get_ports { dphy_hs_clock_clk_p }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=mipi_clk_p
|
||||
#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[0] }]; #IO_L7N_T1_AD2N_35 Sch=mipi_lane_n[0]
|
||||
#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[0] }]; #IO_L7P_T1_AD2P_35 Sch=mipi_lane_p[0]
|
||||
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_n[1] }]; #IO_L11N_T1_SRCC_35 Sch=mipi_lane_n[1]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVDS_25 } [get_ports { dphy_data_hs_p[1] }]; #IO_L11P_T1_SRCC_35 Sch=mipi_lane_p[1]
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cam_clk }]; #IO_L18P_T2_AD13P_35 Sch=cam_clk
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 PULLUP true} [get_ports { cam_gpio }]; #IO_L18N_T2_AD13N_35 Sch=cam_gpio
|
||||
#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { cam_scl }]; #IO_L15N_T2_DQS_AD12N_35 Sch=cam_scl
|
||||
#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { cam_sda }]; #IO_L15P_T2_DQS_AD12P_35 Sch=cam_sda
|
||||
|
||||
|
||||
##Unloaded Crypto Chip SWI (for future use)
|
||||
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L13N_T2_MRCC_34 Sch=crypto_sda
|
||||
|
||||
|
||||
##Unconnected Pins (Zybo Z7-20 only)
|
||||
#set_property PACKAGE_PIN T9 [get_ports {netic19_t9}]; #IO_L12P_T1_MRCC_13
|
||||
#set_property PACKAGE_PIN U10 [get_ports {netic19_u10}]; #IO_L12N_T1_MRCC_13
|
||||
#set_property PACKAGE_PIN U5 [get_ports {netic19_u5}]; #IO_L19N_T3_VREF_13
|
||||
#set_property PACKAGE_PIN U8 [get_ports {netic19_u8}]; #IO_L17N_T2_13
|
||||
#set_property PACKAGE_PIN U9 [get_ports {netic19_u9}]; #IO_L17P_T2_13
|
||||
#set_property PACKAGE_PIN V10 [get_ports {netic19_v10}]; #IO_L21N_T3_DQS_13
|
||||
#set_property PACKAGE_PIN V11 [get_ports {netic19_v11}]; #IO_L21P_T3_DQS_13
|
||||
#set_property PACKAGE_PIN V5 [get_ports {netic19_v5}]; #IO_L6N_T0_VREF_13
|
||||
#set_property PACKAGE_PIN W10 [get_ports {netic19_w10}]; #IO_L16P_T2_13
|
||||
#set_property PACKAGE_PIN W11 [get_ports {netic19_w11}]; #IO_L18P_T2_13
|
||||
#set_property PACKAGE_PIN W9 [get_ports {netic19_w9}]; #IO_L16N_T2_13
|
||||
#set_property PACKAGE_PIN Y9 [get_ports {netic19_y9}]; #IO_L14P_T2_SRCC_13
|
||||
26
uart/build.tcl.in
Normal file
26
uart/build.tcl.in
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
set_param general.maxThreads {{THREADS}}
|
||||
read_vhdl [glob ../{{SRC}}/*.vhdl]
|
||||
read_xdc ../{{CONST}}
|
||||
|
||||
synth_design -part {{PART}} -top {{TOP}}
|
||||
write_checkpoint -force post_synth.dcp
|
||||
report_timing_summary -file timing_syn.rpt
|
||||
|
||||
opt_design
|
||||
place_design
|
||||
phys_opt_design
|
||||
write_checkpoint -force post_place
|
||||
report_timing_summary -file post_place_timing_summary.rpt
|
||||
|
||||
route_design
|
||||
write_checkpoint -force post_route
|
||||
report_timing_summary -file post_route_timing_summary.rpt
|
||||
report_timing -sort_by group -max_paths 100 -path_type summary -file post_route_timing.rpt
|
||||
report_clock_utilization -file clock_util.rpt
|
||||
report_utilization -file post_route_util.rpt
|
||||
report_power -file post_route_power.rpt
|
||||
report_drc -file post_imp_drc.rpt
|
||||
write_verilog -force bft_impl_netlist.v
|
||||
write_xdc -no_fixed_only -force bft_impl.xdc
|
||||
|
||||
write_bitstream -force {{PROJ}}.bit
|
||||
6
uart/program.tcl.in
Normal file
6
uart/program.tcl.in
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
open_hw_manager
|
||||
connect_hw_server
|
||||
current_hw_target
|
||||
open_hw_target
|
||||
set_property PROGRAM.FILE {{PROJ}}.bit [current_hw_device]
|
||||
program_hw_devices [current_hw_device]
|
||||
48
uart/sim/uart_tb.sim.wcfg
Normal file
48
uart/sim/uart_tb.sim.wcfg
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="uart_tb_snapshot.wdb" id="1">
|
||||
<top_modules>
|
||||
<top_module name="uart_tb" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
|
||||
<ZoomEndTime time="148.100001 us"></ZoomEndTime>
|
||||
<Cursor1Time time="28.900000 us"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="164"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="144"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="6" />
|
||||
<wvobject type="logic" fp_name="/uart_tb/clk">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/uart_tb/in_send">
|
||||
<obj_property name="ElementShortName">in_send</obj_property>
|
||||
<obj_property name="ObjectShortName">in_send</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/uart_tb/out_txd">
|
||||
<obj_property name="ElementShortName">out_txd</obj_property>
|
||||
<obj_property name="ObjectShortName">out_txd</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="/uart_tb/U1/U1/baud">
|
||||
<obj_property name="ElementShortName">baud</obj_property>
|
||||
<obj_property name="ObjectShortName">baud</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/uart_tb/U1/U1/transmit_reg">
|
||||
<obj_property name="ElementShortName">transmit_reg[10:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">transmit_reg[10:0]</obj_property>
|
||||
<obj_property name="Radix">BINARYRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="/uart_tb/U1/U1/num_sent">
|
||||
<obj_property name="ElementShortName">num_sent[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">num_sent[3:0]</obj_property>
|
||||
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
34
uart/sim/uart_tb.vhdl
Normal file
34
uart/sim/uart_tb.vhdl
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity uart_tb is
|
||||
end entity;
|
||||
|
||||
architecture behav of uart_tb is
|
||||
|
||||
component uart_top is
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
in_send : in std_logic;
|
||||
out_txd : out std_logic
|
||||
);
|
||||
|
||||
end component;
|
||||
|
||||
signal clk : std_logic := '0';
|
||||
signal in_send : std_logic := '0';
|
||||
signal out_txd : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
clk <= not clk after 4 ns;
|
||||
in_send <= '1' after 16 ns;
|
||||
|
||||
U1: uart_top port map(
|
||||
clk,
|
||||
in_send,
|
||||
out_txd
|
||||
);
|
||||
|
||||
end architecture;
|
||||
36
uart/src/clk_div.vhdl
Normal file
36
uart/src/clk_div.vhdl
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity clk_div is
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk_en : out std_logic
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
architecture behav of clk_div is
|
||||
|
||||
constant DIVIDER : natural := 1084;
|
||||
signal clk_cntr : unsigned(31 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk)
|
||||
then
|
||||
if (clk_cntr = DIVIDER)
|
||||
then
|
||||
clk_en <= '1';
|
||||
clk_cntr <= (others => '0');
|
||||
else
|
||||
clk_en <= '0';
|
||||
clk_cntr <= clk_cntr + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
63
uart/src/pmod_uart.vhdl
Normal file
63
uart/src/pmod_uart.vhdl
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity pmod_uart is
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
in_data : in std_logic_vector(7 downto 0);
|
||||
in_send : in std_logic;
|
||||
|
||||
out_txd : out std_logic
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
architecture behav of pmod_uart is
|
||||
|
||||
component clk_div is
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
clk_en : out std_logic
|
||||
);
|
||||
|
||||
end component;
|
||||
|
||||
signal baud : std_logic := '0';
|
||||
signal transmit_reg : std_logic_vector(10 downto 0) := (others => '0');
|
||||
signal num_sent : unsigned(3 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk)
|
||||
then
|
||||
if (baud = '1') then
|
||||
if (in_send = '1' and num_sent = 0) then
|
||||
transmit_reg(0) <= '0';
|
||||
transmit_reg(8 downto 1) <= in_data;
|
||||
transmit_reg(9) <= '1';
|
||||
|
||||
num_sent <= num_sent + 1;
|
||||
out_txd <= '1';
|
||||
elsif (num_sent /= 0 and num_sent /= 11) then
|
||||
transmit_reg(9 downto 0) <= transmit_reg(10 downto 1);
|
||||
out_txd <= transmit_reg(0);
|
||||
num_sent <= num_sent + 1;
|
||||
else
|
||||
out_txd <= '1';
|
||||
num_sent <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
U1: clk_div port map(
|
||||
clk,
|
||||
clk_en=>baud
|
||||
);
|
||||
|
||||
end architecture;
|
||||
44
uart/src/uart_top.vhdl
Normal file
44
uart/src/uart_top.vhdl
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity uart_top is
|
||||
|
||||
port(
|
||||
clk : in std_logic;
|
||||
in_send : in std_logic;
|
||||
out_txd : out std_logic;
|
||||
led : out std_logic_vector(1 downto 0)
|
||||
);
|
||||
|
||||
end entity;
|
||||
|
||||
architecture behav of uart_top is
|
||||
|
||||
component pmod_uart is
|
||||
port(
|
||||
clk : in std_logic;
|
||||
in_data : in std_logic_vector(7 downto 0);
|
||||
in_send : in std_logic;
|
||||
|
||||
out_txd : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal in_data : std_logic_vector(7 downto 0) := x"45";
|
||||
signal txd : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
U1: pmod_uart port map(
|
||||
clk,
|
||||
in_data,
|
||||
in_send,
|
||||
out_txd => txd
|
||||
);
|
||||
|
||||
led(0) <= in_send;
|
||||
led(1) <= txd;
|
||||
|
||||
out_txd <= txd;
|
||||
|
||||
end architecture;
|
||||
Loading…
Add table
Add a link
Reference in a new issue