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init pmod uart txd

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Luka Jankovic 2025-11-16 23:56:38 +01:00
parent 8e8d2608bf
commit a621ac20aa
12 changed files with 522 additions and 3 deletions
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48
uart/sim/uart_tb.sim.wcfg Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="uart_tb_snapshot.wdb" id="1">
<top_modules>
<top_module name="uart_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0.000000 us"></ZoomStartTime>
<ZoomEndTime time="148.100001 us"></ZoomEndTime>
<Cursor1Time time="28.900000 us"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="164"></NameColumnWidth>
<ValueColumnWidth column_width="144"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="6" />
<wvobject type="logic" fp_name="/uart_tb/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/uart_tb/in_send">
<obj_property name="ElementShortName">in_send</obj_property>
<obj_property name="ObjectShortName">in_send</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/uart_tb/out_txd">
<obj_property name="ElementShortName">out_txd</obj_property>
<obj_property name="ObjectShortName">out_txd</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/uart_tb/U1/U1/baud">
<obj_property name="ElementShortName">baud</obj_property>
<obj_property name="ObjectShortName">baud</obj_property>
</wvobject>
<wvobject type="array" fp_name="/uart_tb/U1/U1/transmit_reg">
<obj_property name="ElementShortName">transmit_reg[10:0]</obj_property>
<obj_property name="ObjectShortName">transmit_reg[10:0]</obj_property>
<obj_property name="Radix">BINARYRADIX</obj_property>
</wvobject>
<wvobject type="array" fp_name="/uart_tb/U1/U1/num_sent">
<obj_property name="ElementShortName">num_sent[3:0]</obj_property>
<obj_property name="ObjectShortName">num_sent[3:0]</obj_property>
<obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
</wvobject>
</wave_config>

34
uart/sim/uart_tb.vhdl Normal file
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library ieee;
use ieee.std_logic_1164.all;
entity uart_tb is
end entity;
architecture behav of uart_tb is
component uart_top is
port(
clk : in std_logic;
in_send : in std_logic;
out_txd : out std_logic
);
end component;
signal clk : std_logic := '0';
signal in_send : std_logic := '0';
signal out_txd : std_logic;
begin
clk <= not clk after 4 ns;
in_send <= '1' after 16 ns;
U1: uart_top port map(
clk,
in_send,
out_txd
);
end architecture;