From 856eb0951e474d2fd42f7e15e5e99a71de06eb3d Mon Sep 17 00:00:00 2001 From: Luka Jankovic Date: Mon, 17 Nov 2025 22:49:11 +0100 Subject: [PATCH] initial uart pmod rxd implementation --- uart/Zybo-Z7.xdc | 4 ++-- uart/src/pmod_uart.vhdl | 28 ++++++++++++++++++++++++++++ uart/src/uart_top.vhdl | 11 +++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/uart/Zybo-Z7.xdc b/uart/Zybo-Z7.xdc index c95f3cf..8a0cfb5 100644 --- a/uart/Zybo-Z7.xdc +++ b/uart/Zybo-Z7.xdc @@ -104,7 +104,7 @@ set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] #Pmod Header JA (XADC) #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P +set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P # set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P #set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N @@ -115,7 +115,7 @@ set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led[1] ##Pmod Header JB (Zybo Z7-20 only) #set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1] -set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1] +#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L15N_T2_DQS_13 Sch=jb_n[1] #set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L11P_T1_SRCC_13 Sch=jb_p[2] #set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { out_txd }]; #IO_L11N_T1_SRCC_13 Sch=jb_n[2] #set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L13P_T2_MRCC_13 Sch=jb_p[3] diff --git a/uart/src/pmod_uart.vhdl b/uart/src/pmod_uart.vhdl index 379fb11..1696ecc 100644 --- a/uart/src/pmod_uart.vhdl +++ b/uart/src/pmod_uart.vhdl @@ -9,6 +9,10 @@ entity pmod_uart is in_data : in std_logic_vector(7 downto 0); in_send : in std_logic; + out_data : out std_logic_vector(7 downto 0); + out_done : out std_logic; + + in_rxd : in std_logic; out_txd : out std_logic ); @@ -29,6 +33,9 @@ architecture behav of pmod_uart is signal transmit_reg : std_logic_vector(10 downto 0) := (others => '0'); signal num_sent : unsigned(3 downto 0) := (others => '0'); + signal recv_reg : std_logic_vector(10 downto 0) := (others => '0'); + signal num_recv : unsigned(3 downto 0) := (others => '0'); + begin process(clk) @@ -55,9 +62,30 @@ begin end if; end process; + process(clk) + begin + if rising_edge(clk) + then + if (baud = '1') + then + if (num_recv = 0 and in_rxd = '0') then + num_recv <= num_recv + 1; + elsif (num_recv = 11) then + recv_reg(10 downto 1) <= recv_reg(9 downto 0); + recv_reg(0) <= in_rxd; + num_recv <= (others => '0'); + else + num_recv <= num_recv + 1; + end if; + end if; + end if; + end process; + U1: clk_div port map( clk, clk_en=>baud ); + out_data <= recv_reg(8 downto 1); + end architecture; diff --git a/uart/src/uart_top.vhdl b/uart/src/uart_top.vhdl index e9535af..60b97e5 100644 --- a/uart/src/uart_top.vhdl +++ b/uart/src/uart_top.vhdl @@ -20,6 +20,10 @@ architecture behav of uart_top is in_data : in std_logic_vector(7 downto 0); in_send : in std_logic; + out_data : out std_logic_vector(7 downto 0); + out_done : out std_logic; + + in_rxd : in std_logic; out_txd : out std_logic ); end component; @@ -27,12 +31,19 @@ architecture behav of uart_top is signal in_data : std_logic_vector(7 downto 0) := x"45"; signal txd : std_logic := '0'; + signal out_data : std_logic_vector(7 downto 0); + signal out_done : std_logic; + signal in_rxd : std_logic; + begin U1: pmod_uart port map( clk, in_data, in_send, + out_data, + out_done, + in_rxd, out_txd => txd );